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24LC21A
FIGURE 3-3:
Display Power-on
or
DDC Circuit Powered
from +5 volts
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA ?
The 24LC21A was designed to
comply to the portion of flowchart inside dash box
Communication
is idle
Is Vsync
present?
No
Yes
Send EDID continuously
using Vsync as clock
High-to-Low
transition on
SCL?
Yes
Stop sending EDID.
Switch to DDC2? mode.
Display has
optional
transition state
?
Yes
Set Vsync counter = 0
or start timer
No
No
High-to-Low
transition on
SCL?
Yes
DDC2 communication
idle. Display waiting for
address byte.
DDC2B
address
received?
No
No
Yes
Receive DDC2B
command
No
Change on
SCL, SDA or
Reset counter or timer
Respond to DDC2B
command
VCLK lines?
Yes
Is display
No
No
High-Low
transition on SCL
?
Yes
Access.bus TM
capable?
Yes
Reset Vsync counter = 0
Valid
DDC2 address
received?
No
Yes
Valid Access.bus
address?
Yes
No
No
No
VCLK
cycle?
Yes
Increment VCLK counter
(if appropriate)
Counter=128 or
See Access.bus
specification to determine
correct procedure.
timer expired?
Yes
Switch back to DDC1?
mode.
Note 1: The base flowchart is copyright ? 1993, 1994, 1995 Video Electronic Standard Association (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A.
DS21160G-page 6
? 2008 Microchip Technology Inc.
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相关代理商/技术参数
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功能描述:电可擦除可编程只读存储器 2.5V Dual Mode RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
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24LC21AT/SN-CUT TAPE
制造商:Microchip 功能描述:24LC21 Series 1 Kb I2C 2 Wire (128 x 8) 2.5V Serial EEPROM SMT - SOIC-8